Table of Contents
Advanced Concepts in VHDL
RASSP Roadmap
Module Goals
Outline
Outline (cont.)
Advantages of Using VHDL
Outline
Fundamental View of VHDL
Aliases
Alias An Example
Foreign Interfaces
Foreign Interfaces An Example
Files
File Opening and Closing
Text Input and Output
TEXTIO Procedures
Using TEXTIO
TEXTIO An Example
Assert Statement
Assert Statements
Assert Statements An Example
Processes Revisited
Processes Revisited (Cont.)
Signal Assignment Statements Revisited (Cont.)
Signal Assignment Statements Revisited (Cont.)
Signal Assignment Statements Revisited (Cont.)
Signal Assignment Statements Revisited (Cont.)
Named Associations
Shared Variables
Shared Variables Non-determinism
Shared Variables Stack Example
Shared Variables Stack Example
Outline
Abstract Data Type Example
Abstract Data Types An Example Package Declaration
Abstract Data Types An Example Package Body
Example From UVA ADEPT
Example From UVA ADEPT Bus Resolution Function
Example From UVA ADEPT UVA Package Declaration
Example From UVA ADEPT UVA Package Declaration (Cont.)
Example From UVA ADEPT UVA Package Body
Example From UVA ADEPT UVA Package Body (Cont.)
Example From UVA ADEPT UVA Package Body (Cont.)
Example From UVA ADEPT UVA Package Body (Cont.)
Simple Module Examples Source Module
Simple Module Examples Fixed_Delay Module
Simple Module Examples Sink Module
Three Module Example Testbench Description
Three Module Example Simplified Event Sequence
Three Module Example Detailed Event Sequence
Outline
Summary
References
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