Slide 22 of 53
The full syntax of the VHDL process statement is shown here. Two important points are made in this slide.
First, the notion of a passive process is introduced. Because passive processes do not create events in the VHDL timing cycle (i.e. they do not make signal assignments), they may be included in VHDL entity declarations where they may be used with TEXTIO or assert statements to report on the state of a simulation, for example.
Second, the postponed process was introduced in VHDL93 to allow a modeler to implement processes that will not be executed until the last possible moment in the simulation cycle. Postponed processes may be used to allow transient conditions to settle out before a simulation state is examined or an assignment is made. Note that any signal assignment in a postponed process must include an assigned delay (i.e. cannot default to a delta cycle delay) to prevent the addition of further delta cycles within the simulation cycle such that the delta cycle in which the postponed process executed would no longer be the last of the simulation cycle.