Rules for Actuals and Locals
An actual is either signal declared within the architecture or a port in the entity declaration
- A port on a component is known as a local and must be matched with a compatible actual
VHDL has two main restrictions on the association of locals with actuals
- Local and actual must be of same data type
- Local and actual must be of compatible modes
- Locally declared signals do not have an associated mode and can connect to a local port of any mode
Locals are defined as the ports of the component, and actuals are the signals visible within an architecture. VHDL has two restrictions on the association of locals with actuals.
1) The local and actual must be of the same data type.
2) The local and actual must be of compatible modes. An actual of mode IN (i.e. a PORT of mode IN since locally declared signals do not have a mode) can only be associated with an local of mode IN, and an actual of mode OUT (i.e. a PORT of mode OUT) can only be associated with a local of mode OUT. A local INOUT port is generally associated with an INOUT or OUT actual. Locally declared signals can be connected to locals of any mode, but care must be exercised to avoid illegal connections (e.g. a single actual connected to two mode OUT locals).