Summary of Concepts of Structural VHDL

• Various levels of abstraction supported in description of VHDL structural models

  • Direct instantiation requires detailed knowledge of building blocks when they are incorporated
  • Use of components allows definition and use of idealized local building blocks
    • Can define local interface for component to be connected to local signals
    • Declared components bound to VHDL design objects (i.e. entity/architecture descriptions)
      • Binding done either locally or deferred to higher levels in design hierarchy via use of configurations

• Actuals and locals must be of compatible types and modes

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In summary, structural VHDL is concerned with the interconnection and arrangement of components describing the contents of a design. The behavior of the underlying design objects, therefore, is not explicitly indicated. A structural description can be thought of as a physical netlist describing a hierarchical representation of a VHDL model.