Using Direct Instantiation
ARCHITECTURE struct_1 OF reg4 IS
CONSTANT enabled : level := '1';
r0 : ENTITY work.dff(behav)
PORT MAP (d0,clk,enabled,q0,OPEN);
r1 : ENTITY work.dff(behav)
PORT MAP (d1,clk,enabled,q1,OPEN);
r2 : ENTITY work.dff(behav)
PORT MAP (d2,clk,enabled,q2,OPEN);
r3 : ENTITY work.dff(behav)
PORT MAP (d3,clk,enabled,q3,OPEN);
Provides one-step mechanism for plugging in previously defined VHDL design objects
Only available one level up in hierarchy from level of incorporated building block(s)
Notes:
The direct instantiation method was introduced in VHDL-93. It allows a VHDL design object to be plugged in directly to an architecture’s description by connecting local signals to its interface. This mechanism does not require the use of an idealized component to be declared, instantiated, and bound. Rather, a VHDL entity/architecture object may be inserted into an architecture description in one step.