VHDL ObjectsSignals vs Variables
A key difference between variables and signals is the assignment delay
ARCHITECTURE sig_ex OF test IS
To review, note that some delay must transpire after a VHDL signal assignment statement before the signal assumes its new value. Examples will be used in this and the next slide to illustrate the difference between signals and variables. The example shown above utilizes signals. Note that in this example, a, b, c, out_1, and out_2 are signals that are declared elsewhere, e.g. in the componentís entity.
The table indicates the values for the various signals at the key times in the example. At time 1, a new value of 1 is observed on a. This causes the process sensitivity list to fire and results in a 0 being assigned to out_1. The signal assignment statement for out_2 will also be executed but will not result in a new assignment to out_2 because neither out_1 nor c will be changed at this time. At time 1+d (i.e. 1 plus 1 delta cycle), out_1 assumes its new value causing the process sensitivity list to fire again. In this process execution, the statement for out_1 will be executed again but no new assignment will be made because its right hand side parameters have not changed. The out_2 assignment statement, however, results in a 1 being assigned to out_2. At time 1+2d, out_2 assumes its new value of 1. This example, then, requires 2 delta cycles and two process executions to arrive at its quiescent state following a change to a (or b, for that matter).