VHDL Objects Signals vs Variables (Cont.)
ARCHITECTURE var_ex OF test IS
In this example, variables are used to achieve the same functionality as the example in the previous slide. In this example, however, when there is a change in a at time 1, out_3 will assume its new value at time 1 because it is a variable, and VHDL variable assignment statements result in the new values being assumed immediately. The new value for out_4, therefore, will be calculated with the new out_3 value and results in an assignment to a value of ‘1’ being scheduled for one delta cycle in the future.
Also note, however, that in this example, the order in which the statements appear within the process is important because the two statements are executed sequentially, and the process will only be executed once as a result of the single change in a.