General Steps to Incorporate VHDL Design Objects
A VHDL design object to be incorporated into an architecture must generally be :
- declared -- where a local interface is defined
- instantiated -- where local signals are connected to the local interface
- Regular structures can be created easily using GENERATE statements in component instantiations
- bound -- where an entity/architecture object which implements it is selected for the instantiated object
The three steps shown above illustrate the general requirements for incorporating design objects. It is important to note that the direct instantiation method illustrated in the next slide skips the declaration of a local component and combines the instantiation and binding into a single statement.
Also note that binding may be postponed to higher levels in the design hierarchy to provide flexibility in the selection of design objects to be incorporated.