4-Bit Register as Running Example
GENERIC(tprop : delay := 8 ns;
ARCHITECTURE behav OF dff IS
-- first, check for rising clock edge
-- and check that ff is enabled
IF ((clk = '1' AND clk'LAST_VALUE = '0')
-- now check setup requirement is met
-- now check for valid input data
ELSE -- else invalid data
ELSE -- else setup not met
- First, need to find the building block(s)
- Reusing an object from examples in Module 10
Notes:
As a running example, we will build a 4-bit register using the D flip-flop model presented in Module 10, the Basic VHDL Module.