The following example shows how attributes can be used to make an 8-bit register
- Triggers on rising clock edge
- Latches only on enable high
- Has a data setup time of x_setup
- Has propagation delay of prop_delay
GENERIC (x_setup, prop_delay : TIME);
PORT(enable, clk : IN qsim_state;
a : IN qsim_state_vector(7 DOWNTO 0);
b : OUT qsim_state_vector(7 DOWNTO 0));
- qsim_state type is being used - includes logic values 0, 1, X, and Z
The example presented on this and the next three slides is a simple rising clock edge triggered 8-bit register with an active-high enable. The register has a data setup time of x_setup and a propagation delay of prop_delay.
The input and output signals of this register use the QSIM_STATE logic values. These values include logic 0, 1, X and Z. The a and b signals use the QSIM_STATE_VECTOR type which is an array of QSIM_STATE type vectors.