Slide 75 of 93
The example presented on this and the next three slides is a simple rising clock edge triggered 8-bit register with an active-high enable. The register has a data setup time of x_setup and a propagation delay of prop_delay.
The input and output signals of this register use the QSIM_STATE logic values. These values include logic 0, 1, X and Z. The a and b signals use the QSIM_STATE_VECTOR type which is an array of QSIM_STATE type vectors.