VHDL Design ExampleBehavioral Specification
A high level description can be used to describe the function of the adder
- The model can then be simulated to verify correct functionality of the component
ARCHITECTURE half_adder_a OF half_adder IS
In the first stage of the design process, a high level behavior of the adder is considered. This level uses abstract constructs (such as the IF-THEN-ELSE statement) to make the model more readable and understandable.
Simulation of the adder at this level shows correct understanding of the problem specifications of the adder. VHDL code for this adder will be shown later.