VHDL Design ExampleData Flow Specification
A second method is to use logic equations to develop a data flow description
- Again, the model can be simulated at this level to confirm the logic equations
ARCHITECTURE half_adder_b OF half_adder IS
carry <= enable AND (x AND y);
result <= enable AND (x XOR y);
An alternative method for describing the functionality of the component is to use data flow specifications with concurrent signal assignment statements. An example of this is shown in the representation here which uses logic equations to describe functionality of the carry and result outputs. Notice that the sequential IF-THEN-ELSE statement cannot be used here (i.e. outside a process).