Slide 44 of 93
In this example, each signal assignment requires one delta cycle delay before the signal assumes its new value. Also note that more than one process can be executed in the same simulation cycle (e.g. both the NAND process and the AND process are executed during delta 2).
Following the sequence of events defined by the VHDL simulation cycle, the 1-0 transition on IN allows the INVERTER process to be executed which results in a 0-1 transition being scheduled on A one delta cycle in the future. The INVERTER process then suspends. Since all process are suspended, simulation time advances by one delta cycle so that A can assume its new value.
The new value of A allows the NAND and AND processes to be executed. Because the value of A will not change again during simulation time delta 2, it doesn’t matter whether NAND or AND is evaluated first. In either case, the NAND process leads to a 1 being scheduled for C and a 0 being scheduled for B, both one delta cycle in the future. After the assignments are scheduled, NAND and AND suspend again. Again, simulation time advances by one delta cycle so that B and C can assume their new values.
The new value of B causes the AND process to be evaluated again. This time, a 0 value is scheduled to be assigned to C one delta cycle in the future, and the AND process can then suspend. Finally, simulation time advances by one delta cycle so that C can assume its new, and final value.
Based on [Perry94], pp 22-24