Basic VHDL RASSP Education & Facilitation Module 10 Version 2.02

6/17/99


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Table of Contents

Basic VHDL RASSP Education & Facilitation Module 10 Version 2.02

RASSP Roadmap

Module Goals

Module Outline

Module Outline (Cont.)

PPT Slide

VHDL Education Coverage

Reasons for Using VHDL

VHDLís History

VHDLís History (Cont.)

Gajski and Kuhnís Y Chart

Representation of a RASSP System

Graphical Representation of the Model Levels using the RASSP Taxonomy

Graphical Representation of the Model Levels using the RASSP Taxonomy (Cont.)

Graphical Representation of the Model Levels using the RASSP Taxonomy (Cont.)

Graphical Representation of the Model Levels using the RASSP Taxonomy (Cont.)

Additional Benefits of VHDL

Putting It All Together

Module Outline

VHDL Design Example

VHDL Design Example Entity Declaration

VHDL Design Example Behavioral Specification

VHDL Design Example Data Flow Specification

VHDL Design Example Structural Specification

VHDL Design Example Structural Specification (Cont.)

VHDL Design Example Structural Specification (cont.)

PPT Slide

VHDL Model Components

VHDL Model Components (cont.)

Entity Declarations

Entity Declarations Port Clause

Entity Declarations Port Clause (cont.)

Entity Declarations Generic Clause

Architecture Bodies

Structural Descriptions

Behavioral Descriptions

Timing Model

Delay Types

Transport Delay

Inertial Delay

Inertial Delay (cont.)

Delta Delay

Delta Delay An Example without Delta Delay

Delta Delay An Example with Delta Delay

PPT Slide

Data Types

VHDL Data Types Scalar Types

VHDL Data Types Scalar Types (Cont.)

VHDL Data Types Scalar Types (Cont.)

VHDL Data Types Scalar Types (Cont.)

VHDL Data Types Composite Types

VHDL Data Types Composite Types (Cont.)

VHDL Data Types Composite Types (Cont.)

VHDL Data Types Access Type

VHDL Data Types Subtypes

VHDL Data Types Summary

VHDL Objects

VHDL Objects Constants

VHDL Objects Variables

VHDL Objects Signals

Signals and Variables

VHDL Objects Signals vs Variables

VHDL Objects Signals vs Variables (Cont.)

VHDL Objects Files

Simulation Cycle Revisited Sequential vs Concurrent Statements

Concurrent Statements

Sequential Statements

Packages and Libraries

Packages

Packages Declaration

Packages Package Body

Packages Use Clause

Libraries

Attributes

Attributes Register Example

Attributes Register Example (Cont.)

Attributes Register Example (Cont.)

Operators

Operators Examples

PPT Slide

Examples

Global Package

Two Input AND Gate Example

And Gate Simulation Results

Tri-State Buffer Example

Tri-State Buffer Simulation Results

D Flip Flop Example

D Flip Flop Simulation Results

PPT Slide

Summary

Putting It All Together

References

References

Author: Robert Klenke

Email: rhklenke@vcu.edu

Home Page: http://saturn.vcu.edu/~rhklenke

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