ADK Cell Library-based Design From Verilog Synthesis

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1. Create a behavioral Verilog description of the chip1 design

1.1 If not already there, move back to your tutorial directory:
>> cd egre429
>> mkdir lab7
>>cd lab7
 
1.2 Open a new VHDL file called adder.vhd and using your favorite text editor and enter the following VHDL description into the file:



 
For more details on the Verilog syntax supported for synthesis, see the Leonardo Spectrum HDL Synthesis Guide (/mentor/exemplar/doc/hdl_syn.pdf).
1.3 Compile the VHDL file:
 
>>vlib work
>>vmap work ./work
>>vlog adder.v
 
You should see the following lines printed out with no errors:

Model Technology ModelSim EE vlog 5.3d Compiler 2000.02 Feb  4 2000
-- Compiling module adder1

Top level modules:
        adder1

2. Simulate the Verilog model

The Verilog model should be functionally simulated to ensure correct operation before it is synthesized.
2.1 Invoke the ModelSim simulator on the adder1 design:
>>vsim adder1
 
2.2 You should see a display like the one below:

 
2.3 Use the View->Signals... menu item to bring up the Signals display. Use the View->Wave->Signals in design menu item in the Signals window to create a Wave window. Finally, force values on each of the input signals using the Force... menu item in the Signals window and run the simulation using the Run->100ns menu item in the main window. The resulting Wave window should look like this:



 

2.4 Exit the ModelSim simulator using the File->Quit menu item in the main window.

3. Synthesize the VHDL models to ADK parts

3.1 Invoke the Exemplar Leonardo synthesis tool:
>>leonardo &
 
A Leonardo Spectrum window like the one below should appear.

Click off the Run Wizard at Startup button in the INPUT FILES box and click Cancel.

3.3 Use the Tools->Variable Editor... item from the pull down menus to bring up the System Variables dialog box. Select the edifout_power_ground_style_is_net variable and set it to TRUE. Use the same method to set the max_fanout_load variable to 14, the force_user_load_values variable to TRUE, the vhdl_write_component_package variable to FALSE, and the vhdl_write_use_packages variable to library IEEE, adk; use IEEE.STD_LOGIC_1164.all; use adk.all;

Note that you can use a transcript file in Leonardo to set these variables faster for you in the future.

 3.4 In the main window, click on the  button in the Quick Setup tab  and select the adder.v file. Select ASIC->ADK->ami0.5(fast) in the Technologies box. Make sure that the  Insert I/O Pads  button is off. Select the Output tab and make set the Format to EDIF. Go back to the Quick Setup tab and click the Run button.

Note that only a simple area optimization was done during the synthesis process. If more complex optimizations, including optimizations for speed, are desired, consult the Leonardo Spectrum User's Guide for details (/mentor/exemplar/leo_user.pdf).

3.5 Click on the output tab and set the Format item to Verilog. Make sure that you change the filename to adder_1.v or Leonardo will overwrite your Verilog source file! After you have confirmed that you have changed the name in the Filename item, click Write.
 

3.6 Exit Leonardo by using the File->Exit menu item in the Leonardo Spectrum window.
 

4. Simulate the synthesized design in Verilog to be sure it functions correctly

After the Verilog model is synthesized, it is always a good idea to functionally simulate the resulting design to ensure it functions correctly and the output matches the behavioral description. There are some legal, synthesizable Verilog constructs that, when synthesized, will not produce the same output as the functional description and synthesis tools have been know on rare occasions to produce incorrect results...

4.1 Map the compiled library of Verilog descriptions for the ADK parts into the proper location to compile the post-synthesis structural description (this library has been pre-compiled for you):

>>vmap adk $ADK/lib/adk_verilog

4.2 Compile the VHDL structural description:

>>vcom adder_1.vhd

4.3 Simulate the structural description of the adder:

>>vsim adder1 -L adk

Use the View->Signals... menu item to bring up the Signals display. Use the View->Wave->Signals in design menu item in the Signals window to create a Wave window. Finally, force values on each of the input signals using the Force... menu item in the Signals window and run the simulation using the Run->100ns menu item in the main window. The resulting Wave window should look like this:

5. Create a symbol and schematic for the synthesized part

After the Verilog model is synthesized, a new symbol and schematic will be generated for it. If the part is synthesized in the same directory as the Verilog description, the new symbol will overwrite the old one, making it difficult to go back and resimulate the Verilog model if it is necessary to change it. To avoid this problem, it is best to generate the symbol and schematic in a separate directory.

5.1 Create a directory called "netlist" (the name isn't important) to hold the symbol and schematic:

>>mkdir netlist
>>cd netlist

 
Now it is possible to copy the EDIF netlist source file into this directory, but then if changes are necessary, keeping both copies updated to the latest version can be a problem. Therefore, it is better to create a Unix link to the original source code in this directory. That way, only one copy of the source code exists and version control is not a problem:

>>ln -s ../adder.edf


The edif2eddm command reads in the EDIF file created by Leonardo and creates a Mentor Graphics database and for the design. The database is placed under a new directory called "work."
 

5.2 Invoke the edif2eddm tool on the adder1.edf file generated by Leonardo :
>>edif2eddm adder.edf
 
Invoke DA to generate a symbol for the synthesized part:
>>adk_da &
5.3 Click on the Open Symbol button and use the Navigator... button in the Open Symbol dialog box to go into the "work" directory and select the adder1 component. Click OK in the Open Symbol dialog box.
5.4 A symbol window will open and a symbol for the synthesized adder1 part will be created within it. The resulting symbol should look like the one below. You may want to use the Properties->Add->Add Single Property... item from the pop up menus to add comp and inst properties to the symbol before you check and save it.

5.5 Check and Save the symbol and exit DA .

5.6 Now you will use the Mentor Graphics schematic generator (sg) tool to generate a schematic for the design from the netlist. Invoke the sg tool:
>>sg &
5.7 Use the File->Open Design from Viewpoint... menu item to bring up the Open Design from Viewpoint dialog box. Click on the Navigator... button and go into the "work" directory and into the adder1 component. Select the adder1 component with the  folder next to it and click OK in the Open Design from Viewpoint dialog box. A blank schematic window will appear in the sg tool window.

9.2 Use the Setup->Symbol->Use Genlib Classification menu item to setup the symbol classifications and then use the Partition Setup... command from the pop up menus (right mouse button) to bring up the Partition Setup dialog box. Click on the Number of Sheets button, make sure the Number of Sheets item is set to 1 and click OK . Use the Generate item from the pop up menus to generate a schematic like the one below:




9.3 Use the File->Save menu item to save the schematic and exit the sg tool.

The schematic created uses ADK library parts which have an underlying transistor-level design and an IC layout associated with them. You can now use the schematic of the synthesized design to perform a transistor-level functional simulation with Accusim (recommended) as described in lab 1, or proceed to ICStation and layout the design using either manual or fully automated placement and routing as described in lab 8.