nexsw Project Status (09/03/2008 - 16:28:01)
Project File: nexsw.ise Current State: Programming File Generated
Module Name: stopwatch
  • Errors:
No Errors
Target Device: xc3s500e-4fg320
  • Warnings:
No Warnings
Product Version: ISE 10.1.01 - Foundation
  • Routing Results:
All Signals Completely Routed
Design Goal: Balanced
  • Timing Constraints:
All Constraints Met
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
(Timing Report)
 
nexsw Partition Summary [-]
No partition information was found.
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 83 9,312 1%  
Number of 4 input LUTs 116 9,312 1%  
Logic Distribution     
Number of occupied Slices 92 4,656 1%  
    Number of Slices containing only related logic 92 92 100%  
    Number of Slices containing unrelated logic 0 92 0%  
Total Number of 4 input LUTs 166 9,312 1%  
    Number used as logic 116      
    Number used as a route-thru 50      
Number of bonded IOBs 19 232 8%  
Number of BUFGMUXs 1 24 4%  
 
Performance Summary [-]
Final Timing Score: 0 Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentWed Sep 3 15:40:46 2008000
Translation ReportCurrentWed Sep 3 16:24:10 2008000
Map ReportCurrentWed Sep 3 16:25:00 2008002 Infos
Place and Route ReportCurrentWed Sep 3 16:26:30 2008002 Infos
Static Timing ReportCurrentWed Sep 3 16:27:02 2008003 Infos
Bitgen ReportCurrentWed Sep 3 16:27:34 2008000

Date Generated: 09/03/2008 - 16:28:02