VHDL provides sophisticated constructs making it a versatile description language for modeling of hardware structure and behavior, e.g. :
- Bus resolution functions allow for user defined bus arbitration
- Shared variables, new to VHDL 93, support sharing of information in abstract models
This concludes the sequence of VHDL modules developed by the RASSP E&F team
- These modules are introductory in nature and are not intended to provide a complete and comprehensive coverage of VHDL
- The contents of these modules, however, provide enough information to allow a designer new to VHDL to successfully describe complex systems with VHDL
This instructional module has illustrated the versatility of VHDL in supporting abstraction and information encapsulation to facilitate the description of complex systems. Example system design and description methodologies based on VHDL were included primarily to illustrate the VHDL constructs used to support modeling at higher levels of design abstraction.