Three Module ExampleTestbench Description

LIBRARY uvalib;

USE uvalib.uva.ALL;

ENTITY Test IS

END;

ARCHITECTURE Ar_Test OF Test IS

SIGNAL A,B : Token_Res;

BEGIN

m0 : ENTITY work.Source(Ar_Source)

GENERIC MAP (5ns)

PORT MAP (A);

m1 : ENTITY work.FD(Ar_FD)

GENERIC MAP (5ns)

PORT MAP (A,B);

m2 : ENTITY work.Sink(Ar_Sink)

PORT MAP (B);

END Ar_Test;

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This slide shows the top level VHDL description in which the three modules just described are instantiated and connected to each other by their PORT MAP assignments.