In VHDL87, the scope of a variable was limited to the process in which it was declared
- Signals were the only means of inter-process communication
VHDL93 introduced the shared variable
- Available to many processes or procedures
Shared variables are useful for system level modeling or object-oriented programming
- Shared variables also introduce some non-determinism in VHDL, limiting the uses of this new construct
VHDL87 limited the scope of the variable to the process in which it was declared. Signals were the only means of communication between processes, but signal assignments require an advance in either delta time or simulation time.
VHDL '93 introduced shared variables which are available to more than one process. Like ordinary VHDL variables, their assignments take effect immediately. However, caution must be exercised when using shared variables because multiple processes making assignments to the same shared variable can lead to unpredictable behavior if the assignments are made concurrently. The VHDL ‘93 standard does not define the value of a shared variable it two or more processes make assignments in the same simulation cycle.