Signal Assignment StatementsRevisited (Cont.)

• Signal assignment statement syntax :

• Delay_mechanism is either :
  • TRANSPORT
    • all input events reflected on output
  • REJECT time_expression INERTIAL
    • used to model component inertia so that short pulses on input signals do not affect the target output
    • default delay_mechanism if none is specified
      -- default condition further specifies that the provided propagation delay be used for both the REJECT and INERTIAL delays in the assignment
      

[label :] target <= [delay_mechanism] waveform;

Previous slide

Next slide

Back to first slide

View graphic version

In this section, signal assignment statements are revisited paying special attention to both the similarities and the differences between concurrent and sequential signal assignment statements.

The delay_mechanism construct is common to both concurrent and sequential signal assignment statements. It provides flexibility in determining the response to changes to input signals.