Assert StatementsAn Example
This code has similar functionality to that of the TEXTIO example
- Assume good = ‘1’, reset = ‘0’
Possible actions associated with the various SEVERITY levels are simulator dependent
- E.g. simulation may stop if a FAILURE assertion triggers
PROCEDURE display_state (current_state : IN state) IS
ASSERT NOT(current_state = good)
REPORT “Status of State: good”
ASSERT NOT(current_state = reset)
REPORT “Status of State: reset”
The example shown here provides a similar functionality to the TEXTIO example shown previously. The ASSERT statements are used to display the current state of a FSM. Note that these ASSERT statements are concurrent. ASSERTs can be concurrent or sequential depending on whether they appear inside or outside VHDL processes. ASSERTs can also be put in entity statements.
While this procedure does a similar job to the TEXTIO example, it can provide more information to the user and the simulator. The SEVERITY level may cause the simulator to pause or stop altogether. While these definitions are implementation defined, they can be useful.