Model description may include portions written in a foreign programming language (e.g. C)
- Subprogram or architecture body can be described in programming language other than VHDL
- Designer can incorporate previously written code or code that is difficult to write in VHDL
Details on use of foreign code is largely implementation dependent
Not possible to include variables, signals, or entities described in a foreign language
ATTRIBUTE FOREIGN OF name: construct IS "information/parameters";
VHDL allows the functionality of architecture bodies and subprograms to be described in a foreign language (e.g. C) and interfaced to a VHDL model. For example, foreign code may be used when it is difficult to implement the same functionality in VHDL, such as in cases where complex arithmetic functions not directly available in VHDL are required.
The interface between VHDL and foreign code is simulator implementation dependent. VHDL passes the parameters to the foreign code but has no further information about the foreign code. The use and structure of foreign code is largely up to the particular simulator implementation.