Aliases
Aliases can significantly improve the readability of VHDL descriptions by using a shorthand notation for names
Aliases allow reference to named items in different ways:
ALIAS Data_Bus: MVL_Vector(7 DOWNTO 0) is Data_Word(15 DOWNTO 8);
Aliases can rename any named item except labels, loop parameters, and generate parameters
Notes:
VHDL provides the alias construct to enhance readability in VHDL descriptions. Aliases are available in two varieties:
1. Object aliases rename objects
2. Non-object aliases rename items that are not objects