Fundamental View of VHDL
Fundamentally, VHDL follows event-driven concurrent execution semantics :
- Sequential execution available inside processes
- Note component instantiations are concurrent statements
ARCHITECTURE arch_label OF ent_label IS
[architecture_declarations]
[concurrent_procedure_call_statement] |
[concurrent_assertion_statement] |
[concurrent_signal_assignment_statement] |
[component_instantiation_statement] |
Notes:
By this time, the student should recognize that VHDL is actually a concurrent language in which consistent and predictable behavior is enforced by the underlying timing model. Sequential behavior is available within processes to facilitate the description of complex functionality that is more easily implemented with sequential statements, but each process is then itself a concurrent statement within VHDL.