Unsigned 8 Bit Multiplier Control Unit(Architecture - State Transition Process)

STATE_TRANS : PROCESS(present_state,present_count,start,q0)

BEGIN

next_state <= present_state; -- default case

next_count <= present_count; -- default case

CASE present_state IS

WHEN idle =>

IF(start = '1') THEN

next_state <= initialize;

ELSE

next_state <= idle;

END IF;

next_count <= present_count;

WHEN initialize =>

next_state <= test;

next_count <= present_count;

WHEN test =>

IF(present_count < 8) THEN

IF(q0 = '0') THEN

next_state <= shift;

ELSE

next_state <= add;

END IF;

ELSE

next_state <= idle;

END IF;

next_count <= present_count;

WHEN add =>

next_state <= shift;

next_count <= present_count;

WHEN shift =>

next_state <= test;

next_count <= present_count + 1;

WHEN OTHERS =>

next_state <= idle;

next_count <= present_count;

END CASE;

END PROCESS STATE_TRANS;

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This is the state transition process for the state machine. Note the default assignment of next_state = present_state which is only really required for (some) synthesis tools.