Unsigned 8 Bit Multiplier Control Unit(Architecture - Clock Process)
ARCHITECTURE state_machine OF mult_controller_behav IS
SUBTYPE count_integer IS INTEGER RANGE 0 TO 8;
TYPE states IS (idle,initialize,test,shift,add);
SIGNAL present_state : states := idle;
SIGNAL next_state : states := idle;
SIGNAL present_count : count_integer := 0;
SIGNAL next_count : count_integer := 0;
CLKD : PROCESS(clk,reset)
ELSIF(clk'EVENT AND clk = '1' AND clk'LAST_VALUE = '0') THEN
present_state <= next_state;
present_count <= next_count;
This is the beginning of the architecture of the control unit. Note that the constrained subtype of integer is for synthesis - unconstrained integers are hard to synthesize! Also note the state variables are enumerated types. This allows the synthesis tools to encode the state variable using different schemes.
Also included here is the clock process. Note that it is edge triggered and that both present_state and present_count are updated on the clock edge. Also note the asynchronous reset signal.