Unsigned 8 Bit Multiplier Control Unit Behavioral Description

• Synthesizable VHDL state machine description

• Two internal state variables

  • present_state
  • present_count

• Three interacting VHDL processes

  • Clock (or register) process
  • State Transition process
  • Output process

• Moore machine

• Asynchronous reset signal and synchronous start signal

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The state machine actually has two state variables, the current state of the control state machine (e.g., initialize, shift, add), and the present loop count. The loop count is a state variable in that it has a present value and a next value, and it is updated in the clock process. However, the value of count only affects the next control state the machine goes to and doesn’t affect the outputs. The implementation is actually more like two state machines in the same architecture.