Potential Problems to Avoid
Objects defined by subtypes derived from a base type are considered to be of the same type
PROCESS
SUBTYPE smallintA IS INTEGER RANGE 0 TO 10;
SUBTYPE smallintB IS INTEGER RANGE 0 TO 15;
VARIABLE A: smallintA := 5;
VARIABLE B: smallintB := 8;
VARIABLE C: INTEGER;
BEGIN
B := B * A; -- OK
C := B + 1; -- OK
END;
Notes:
Interestingly, even though VHDL is considered to be strongly typed, the developers of the language decided to strongly type only with respect to the base type, not derived subtypes.
Thus, the VHDL analyzer will not be aware of inconsistent subtypes in the example shown here, and the simulator will execute the statements as expected. Note, however, that the result after multiplying A and B may be out of the range of B's subtype resulting in a runtime subtype range violation.