Packages encapsulate elements that can be globally shared among two or more design units
A package consists of two parts
Necessary definitions for certain objects in package declaration, e.g. subprogram descriptions
VHDL packages are collections of reusable declarations and descriptions of VHDL types, subtypes, subprograms, aliases, constants, attributes, components, etc.
The declaration section of a package contains declaration statement for all the elements in the package. For several elements (e.g. TYPE definitions), the declaration is all that is needed. For some elements, however (e.g. subprograms), a functional description is also needed. This additional information is placed in the body section of the package.