Bus ResolutionSmoke Generator Fixed
A signal which has a bus resolution function associated with it may have multiple drivers
LIBRARY attlib; USE attlib.att_mvl.ALL;
PORT (a, b, c : IN MVL; z : OUT MVL);
ARCHITECTURE fixed OF bus IS
SIGNAL circuit_node : wired_and MVL;
Because the the BRF wired_and is associated with the signal circuit_node above, the VHDL simulator can use the BRF to determine the value to assign to circuit_node even though it has multiple active drivers.