Example Behavioral VHDL Model
USE TEXTIO.all, mypackage.all;
PORT (X, Y: IN BIT; Z: out BIT_VECTOR(3 DOWNTO 0);
ARCHITECTURE behavior OF module IS
SIGNAL A, B: BIT_VECTOR(3 DOWNTO 0);
A(0) <= X AFTER 20 ns; A(1) <= Y AFTER 40 ns;
VARIABLE P, Q: BIT_VECTOR(3 DOWNTO 0);
This slide shows a simple example of a behavioral model. Note that the VHDL process is a key construct in behavioral models and much of this module is devoted to presenting VHDL features associated with processes.