Abstraction levels of VHDL models
- Structural level
- Behavioral/structural mixed (i.e., data flow)
- Functional performance is the goal of behavioral modeling
- Timing optionally included in the model
- Software engineering practices should be used to develop behavioral models
- Structured design
- Iterative refinement
- Abstract data typing
- Loose coupling, strong cohesion
Introduction to Behavioral Modeling in VHDL
Using VHDL, a system designer can model a circuit (i.e. a component or system) at multiple levels of abstraction. In prior lessons, we have concentrated on the basic elements and the structural forms of describing models in VHDL. In this module we concentrate on the behavioral view, i.e. describing how the circuit is to perform.
In behavioral modeling, we are vitally interested in the functionality of the circuit and less interested in its structural composition. At the highest levels of behavioral abstraction, we may even ignore timing.
When modeling in VHDL, it is important to follow standard practices of software engineering. Otherwise, the model may be hard to maintain, even by the person who wrote it. In addition, to aid the reuse of models, even “throw-away” models should be created with care, and with the thought that others may use it.
Typical model design and coding practices include structuring the design, iteratively refining a high-level view of the model down to its final form, and organizing the individual model components so that they are loosely coupled (small number of interface signals) and have strong cohesion (keep strongly related functions in the same architectural body).