Slide 23 of 65
Because VHDL is a rich language, there are several ways to say the same thing. This example illustrates how the concurrent VHDL statements shown on the left side (as procedure calls, actually) are equivalent to the one-statement processes shown on the right. Note that the “sensitivity list” for a process is functionally equivalent to a “wait on” statement at then end of the process (e.g. the process for MakeClock on the right).