Slide 21 of 65
The testbench is the self-contained top level component in the system hierarchy, Therefore, it does not have any I/O pins (I.e. there are not PORT signals in its entity)..
In addition to instantiating the necessary components necessary to describe the system, a testbench may contain a behavioral VHDL description which may be used to generate stimulus patterns to the system as well as expected results which can then be compared with the outputs of the systemís subcomponents.
It should be noted that many modern VHDL simulators provide versatile mechanisms for forcing or driving a VHDL modelís PORT signals via simulation scripts and such, thus making the use of testbenches often unnecessary