Table of Contents
PPT Slide
RASSP Roadmap
Module Goals
Outline
PPT Slide
Example Behavioral VHDL Model
Module Outline
VHDL Processes
Process Syntax
Let’s Write a VHDL Model ...
Full Adder Architecture
Two Full Adder Processes
Complete Architecture
Alternate Carry Process
VHDL Sequential Statements
A Design Example 2-bit Counter
The Wait Statement
Equivalent Processes
“wait until” and “wait for”
Mix and Match
Testbenches
Testbenches (Cont.)
Freedom of Expression
Freedom of Expression (Cont.)
Signal Assignment Statements
Inertial vs Transport Delays
Subprograms
Functions
Functions
Procedures
Procedures (Cont.)
Signal Resolution and Buses
Bus Resolution Smoke Generator
Bus Resolution Functions
Bus Resolution Smoke Generator Fixed
Null Transactions
Entity Statements
Blocks and Guards
Blocks and Guards
VHDL Packages
Packages
Potential Problems to Avoid
Potential Problems to Avoid (Cont.)
Resolving Difficulties
Module Outline
Examples
Package with Bus Resolution Function (Package Declaration)
Package with Bus Resolution Function (Package Body)
Bus Resolution Function Simulation Results
Flow Chart for Unsigned 8 Bit Multiplier Controller
State Diagram for Unsigned 8 Bit Multiplier Controller
Unsigned 8 Bit Multiplier Control Unit Behavioral Description
Unsigned 8 Bit Multiplier Control Unit (Entity)
Unsigned 8 Bit Multiplier Control Unit (Architecture - Clock Process)
Unsigned 8 Bit Multiplier Control Unit (Architecture - State Transition Process)
Unsigned 8 Bit Multiplier Control Unit (Architecture - Output Process)
Full Unsigned 8 Bit Multiplier Simulation Results (Control Unit & Data Path)
Package for Quicksort Routine (Package Declaration)
Package for Quicksort Routine (Package Body - Quicksort Procedure)
Quicksort Routine (Entity & Architecture)
Quicksort Routine (Architecture Cont.)
Quicksort Routine Simulation Results
Module Outline
Summary
References
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