Unsigned 8 Bit Multiplier Data Path (Architecture)

SIGNAL gnd : level := '0';

SIGNAL c_out, a_scan_out, carry_out : level;

SIGNAL a_out, alu_out, m_out

: level_vector(7 DOWNTO 0);

BEGIN

-- A, C, M, and Q registers

A1 : shift_reg8_str GENERIC MAP(6 ns, 1 ns)

PORT MAP(d(0)=>alu_out(0),d(1)=>alu_out(1),

d(2)=>alu_out(2),d(3)=>alu_out(3),

d(4) =>alu_out(4),d(5)=>alu_out(5),

d(6)=>alu_out(6),d(7)=>alu_out(7),

clk => clk, enable => a_enable,

scan_in => c_out, shift => a_mode,

scan_out => a_scan_out,

q(0)=>a_out(0),q(1)=>a_out(1),

q(2)=>a_out(2),q(3)=>a_out(3),

q(4)=>a_out(4),q(5)=>a_out(5),

q(6)=>a_out(6),q(7)=>a_out(7));

C1 : dff GENERIC MAP(5 ns, 1 ns)

PORT MAP( d => carry_out, clk => clk,

enable => c_enable, q => c_out);

M1 : reg8_str GENERIC MAP(4 ns, 1 ns)

PORT MAP(d => multiplicand, clk => clk,

enable => m_enable, q => m_out);

Q1 : shift_reg8_str GENERIC MAP(6 ns,1 ns)

PORT MAP(d(0) => multiplier(0),

d(1) => multiplier(1),

d(2) => multiplier(2),

d(3) => multiplier(3),

d(4) => multiplier(4),

d(5) => multiplier(5),

d(6) => multiplier(6),

d(7) => multiplier(7),

clk => clk,

enable => q_enable,

scan_in => a_scan_out,

shift => q_mode,

q(0) => product(0),

q(1) => product(1),

q(2) => product(2),

q(3) => product(3),

q(4) => product(4),

q(5) => product(5),

q(6) => product(6),

q(7) => product(7));

-- ALU

ALU1 : alu_str GENERIC MAP(8 ns)

PORT MAP(a => m_out, b => a_out,

mode => a_reset,

cin => gnd,

sum => alu_out,

cout => carry_out);

-- connect A register output to product

product(15 DOWNTO 8)<=a_out(7 DOWNTO 0);

END structural;

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This is the component instantiations for the datapath. The mapping of individual bits of the D and Q input and output of the shift registers is necessary to reverse the inputs and outputs. Recall that the shift register was a “shift up” type where the scan_in input goes to D(0) and D(0) to D(6) go to D(1) to D(7) when in shift mode. What is needed for the multiplier is a “shift down” type register where scan_in goes to D(7), etc.

It should have been possible (we believe) to use the syntax

d => multiplier(0 to 7)

in the shift_reg8_str PORT MAP to accomplish the same thing, but the QuickVHDL compiler gave a “warning” and the simulator crashed, so we don’t know if it really should work.