Structural 8 Bit Shift Register Example(Architecture - Generate with If Scheme)

ARCHITECTURE structural OF shift_reg8_str IS

-- COMPONENT DECLARATION

COMPONENT mux2

GENERIC(tprop : delay);

PORT(a : IN level;

b : IN level;

sel : IN level;

c : OUT level);

END COMPONENT;

COMPONENT dff

GENERIC(tprop : delay;

tsu : delay);

PORT(d : IN level;

clk : IN level;

enable : IN level;

q : OUT level;

qn : OUT level);

END COMPONENT;

-- BINDING INDICATIONS

FOR ALL : mux2 USE ENTITY

gate_lib.mux2(behav);

FOR ALL : dff USE ENTITY

gate_lib.dff(behav);

SIGNAL mux_out : level_vector(7 DOWNTO 0);

SIGNAL dff_out : level_vector(7 DOWNTO 0);

BEGIN

-- COMPONENT INSTANTIATION (GENERATE W/ IF)

G1:FOR i IN 0 TO 7 GENERATE

G2 : IF (i = 0) GENERATE

MUX1 : mux2 GENERIC MAP(tprop => tprop/2)

PORT MAP(a => scan_in,

b => d(i),

sel => shift,

c => mux_out(i));

DFF1 : dff GENERIC MAP(tprop => tprop/2,

tsu => tsu)

PORT MAP(d => mux_out(i),

clk => clk,

enable => enable,

q => dff_out(i));

q(i) <= dff_out(i);

END GENERATE G2;

G3 : IF (i > 0) GENERATE

MUX1 : mux2 GENERIC MAP(tprop => tprop/2)

PORT MAP(a => dff_out(i-1),

b => d(i),

sel => shift,

c => mux_out(i));

DFF1 : dff GENERIC MAP(tprop => tprop/2,

tsu => tsu)

PORT MAP(d => mux_out(i),

clk => clk,

enable => enable,

q => dff_out(i));

q(i) <= dff_out(i);

END GENERATE G3;

END GENERATE G1;

scan_out <= dff_out(7);

END structural;

Previous slide

Next slide

Back to first slide

View graphic version

This is the architecture which uses a complex generate statement. There is an IF statement within the generate statement to handle the fact that the mux that is connected to the 0th bit is connected to scan_in instead of the output of the DFF in the previous bit position. Here again, the colors highlight the three parts of the structural description.

Note that the concurrent signal assignment statements to connect the dff_out signal to the Q outputs are inside the generate statements.