Structural 8 Bit Shift Register Example(Entity)
GENERIC(tprop : delay := 15 ns;
PORT(d : IN level_vector(7 DOWNTO 0);
q : OUT level_vector(7 DOWNTO 0));
This is the schematic and entity description for and 8 bit shift register.
Note that in the schematic, signals will be needed between the multiplexor output and the dff’s input and the dff output and the shift register output (Q). The signal on the DFF outputs is needed because it feeds back to the input of the muxes, and that can’t be done by connecting both directly to an output port (until VHDL-93 in which OUT ports are readable inside the architecture). Thus, some concurrent signal assignment statements will be necessary to connect the signal at the dff outputs to the Q outputs.