Structural 8 Bit Register ExampleSimple Generate Statement

LIBRARY gate_lib;

USE gate_lib.resources.all;

ENTITY reg8_str IS

GENERIC(tprop : delay := 8 ns;

tsu : delay := 2 ns);

PORT(d : IN level_vector(7 DOWNTO 0);

clk : IN level;

enable : IN level;

q : OUT level_vector(7 DOWNTO 0);

qn : OUT level_vector(7 DOWNTO 0));

END reg8_str;

ARCHITECTURE structural OF reg8_str IS

-- COMPONENT DECLARATION

COMPONENT dff

GENERIC(tprop : delay;

tsu : delay);

PORT(d : IN level;

clk : IN level;

enable : IN level;

q : OUT level;

qn : OUT level);

END COMPONENT;

-- BINDING INDICATIONS

FOR ALL : dff USE ENTITY gate_lib.dff(behav);

BEGIN

-- COMPONENT INSTANTIATION (GENERATE)

R1:FOR i IN 1 TO 8 GENERATE

I1:dff GENERIC MAP(tprop => tprop,

tsu => tsu)

PORT MAP(d => d(i-1), clk => clk,

enable => enable,

q => q(i-1), qn => qn(i-1));

END GENERATE R1;

END structural;

Qn(0)

Qn(1)

Qn(2)

Qn(7)

Previous slide

Next slide

Back to first slide

View graphic version

This is a structural description of an 8 bit register using DFFs from the library. A simple generate statement is used to instantiate the DFFs and connect them to the individual “bits” at the register’s input and output. The colors highlight the same parts of the structural description as before.