Structural And-Or-Invert Gate Example(Entity)
LIBRARY gate_lib;
USE gate_lib.resources.all;
ENTITY aoi2_str IS
GENERIC(trise : delay := 12 ns;
tfall : delay := 9 ns);
PORT(a : IN level;
b : IN level;
c : IN level;
d : OUT level);
END aoi2_str;
A
B
C
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Notes:
This is the schematic and the VHDL entity description of a simple and-or-invert gate.