-- this uses the and_gate component from before
ARCHITECTURE test_generate OF test_entity IS
SIGNAL S1, S2, S3: BIT_VECTOR(7 DOWNTO 0);
G1 : FOR N IN 7 DOWNTO 0 GENERATE
PORT MAP (S1(N), S2(N), S3(N));
This slide shows an example of the FOR-scheme. The code generates an array of AND gates. In this case, the GENERATE statement has been named G1 and instantiates an array of 8 and_gate components. The PORT MAP statement maps the interfaces of each of the 8 gates to specific elements of the S1, S2, and S3 vectors by using the FOR loop variable as an index.