The binding indication identifies the design object to be used for the component
Two mechanisms available :
- VHDL entity/architecture design object
Binding indication may also include a PORT MAP and/or GENERIC MAP to customize the component(s)
FOR reg4_inst : reg4_comp USE CONFIGURATION work.reg4_conf_1;
FOR ALL : reg1 USE work.dff(behav);
The binding indication identifies the design entity (i.e. entity/architecture object or configuration declaration) to bind with the component and maps the two interfaces together. That is, binding indication associates component instances with a particular design entity. The binding indication may include a PORT MAP and GENERIC MAP to adapt the interfaces of the entity and the component.