Component Binding Specifications
A component binding specification provides binding information for instantiated components
- Single component
- Multiple components
- All components-- All components of this type are effected
- Other components-- i.e. for components that are not otherwise specified
FOR A1 : and_gate USE binding_indication;
FOR A1, A2 : and_gate USE binding_indication;
FOR ALL : and_gate USE binding_indication;
FOR OTHERS : and_gate USE binding_indication;
Unfortunately, component binding specifications are referred to as “configuration specifications” in the VHDL Language Reference Manual, but the term is avoided here to prevent confusion with configuration descriptions.
The component specification can be of several forms, and this slide shows examples for various types. The component specification identifies those components to be configured by name or by the keyword ALL. The keyword OTHERS selects all components not yet configured.