r0 : reg1 PORT MAP (d=>d0,clk=>clk,q=>q0);
The instantiation statement connects a declared component to signals in the architecture
The instantiation has 3 key parts
- Name -- to identify unique instance of component
- Component type -- to select one of the declared components
- Port map -- to connect to signals in architecture
- Along with optional Generic Map presented on next slide
The above example shows an instance of the reg1 component which has been given the name r0. The PORT MAP section of the instantiation indicates how the signals in the interface of the component are assigned to local signals.
Note that in this example, we associated each signal to a port on the component by naming the PORT signals explicitly. VHDL also allows for positional association, but it may only be used if all the signals in a PORT are to be assigned in the order in which they appear in the component declaration.