Power of Configuration Declarations
Reasons to use configuration declarations :
- Large design may span multiple levels of hierarchy
- When the architecture is developed, only the component interface may be available
- Mechanism to put the pieces of the design together
Configurations can be used to customize the use of VHDL design objects interfaces as needed :
- Entity name can be different than the component name
- Entity of incorporated design object may have more ports than the component declaration
- Ports on the entity declaration of the incorporated design object may have different names than the component declaration
As indicated in the previous slide, configuration declarations provide a mechanism for replacing design objects in structural descriptions easily.
Similarly, they allow for structural descriptions to be developed before the entity/architecture building blocks have been finalized. This is particularly useful in a large system which may have been partitioned among several designers.
In addition, idealized components can be made to accommodate actual entity/architecture design object interface requirements in the configuration declaration. This may, for example, be used to tie generics and/or unused signals fixed values (e.g. enable signals to a constant ON value).