Using Component Declarations and Configurations

USE work.resources.all;

ARCHITECTURE struct_3 OF reg4 IS

COMPONENT reg1 IS

PORT (d, clk : IN level;

q : OUT level);

END COMPONENT reg1;

CONSTANT enabled : level := '1';

BEGIN

r0 : reg1 PORT MAP (d<=d0,clk<=clk,q<=q0);

r1 : reg1 PORT MAP (d<=d1,clk<=clk,q<=q1);

r2 : reg1 PORT MAP (d<=d2,clk<=clk,q<=q2);

r3 : reg1 PORT MAP (d<=d3,clk<=clk,q<=q3);

END struct_3;

USE work.resources.all;

CONFIGURATION reg4_conf_1 OF reg4 IS

CONSTANT enabled : level := '1';

FOR struct_3

FOR all : reg1 USE work.dff(behav)

PORT MAP(d=>d,clk=>clk,enable=>enabled,q=>q,qn=>OPEN);

END FOR;

END FOR;

END reg4_conf_1;

-- Architecture in which a COMPONENT for reg4 is declared

...

FOR ALL : reg4_comp USE CONFIGURATION work.reg4_conf_1;

...

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Note that in this example, three separate VHDL files are used. The first file above shows the architecture description in which the reg1 component is declared and instantiated.

The second file shows a configuration declaration in which the reg1 components in the struct_3 architecture of entity reg4 are bound to dff(behav).

The third example shows a small excerpt from an architecture description in which a locally visible component named reg4_comp is bound to a VHDL design object via the configuration declaration reg4_conf_1 found in the work library (i.e. the configuration declaration shown in the middle section of this slide).

Note that the use of configurations to defer the binding of components adds flexibility to structural architecture descriptions by allowing alternative architecture to be plugged in to the design easily.