Mechanisms for IncorporatingVHDL Design Objects

• VHDL mechanisms to incorporate design objects

  • Using direct instantiation (not available prior to VHDL-93)
  • Using component declarations and instantiations
    • Create idealized local components (i.e. declarations) and connect them to local signals (i.e. instantiations)
    • Component instantiations are then bound to VHDL design objects either :
      • Locally -- within the architecture declaring the component
      • At higher levels of design hierarchy, via configurations

• Consider structural descriptions for the following entity :

USE work.resources.all;

ENTITY reg4 IS -- 4-bit register with no enable

GENERIC(tprop : delay := 8 ns;

tsu : delay := 2 ns);

PORT(d0,d1,d2,d3 : IN level;

clk : IN level;

q0,q1,q2,q3 : OUT level);

END reg4;

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There are a number of constructs available in VHDL to incorporate design objects into architecture descriptions. The simplest, but least versatile, is the direct instantiation of a VHDL entity. With this method, the details of the entity’s interface must be known and cannot be customized at instantiation.

The other two mechanisms use a locally declared components to define a idealized element interfaces. A component is then plugged into the architecture description by connecting signals visible in the architecture to the interface of the component in an instantiation statement. The two mechanisms here differ in how a component is bound to an existing VHDL design object. One mechanism binds the component to an existing VHDL entity/architecture object within the architecture description in which the component was instantiated. The second mechanism defers the binding until higher levels in the design hierarchy via the use of configurations which are introduced in this section.