Slide 23 of 43
VHDL provides two different schemes of the GENERATE statement, the FOR-scheme and the IF-scheme. This slide shows the syntax for the FOR-scheme.
The FOR-scheme is reminiscent of a FOR loop used for sequence control in many programming languages. The FOR-scheme generates the included concurrent statements the assigned number of times. In the FOR-scheme, all of generated concurrent statements must be the same. The loop variable is created in the GENERATE statement and is undefined outside that statement (i.e. it is not a variable or signal visible elsewhere in the architecture).
The syntax for the FOR-scheme GENERATE statement is shown in the slide. The loop variable in this case is N. The range can be any valid discrete range. After the GENERATE keyword, the concurrent statements to be generated are stated, and the GENERATE statement is closed with END GENERATE.