D Flip Flop Example
GENERIC(tprop : delay := 8 ns;
ARCHITECTURE behav OF dff IS
-- check for rising clock edge
IF ((clk = '1' AND clk'LAST_VALUE = '0')
AND enable = '1') THEN -- ff enabled
-- first, check setup time requirement
-- check valid input data
ELSE -- else invalid data
ELSE -- else violated setup time requirement
Notes:
This is a DFF example that illustrates the use of signal attributes. Notice the LAST_VALUE attribute is used in the clock statement to recognize a 0 to 1 rising edge transition (the last value has to be a 0 to avoid triggering on X or Z to 1 transitions).
Also, the STABLE attribute is used at each rising clock edge to determine if the d input has satisfied the setup time requirement.